1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device which can reduce a manufacturing cost without dropping a performance of a logic-mixed-DRAM.
2. Description of the Related Art
A logic-mixed-DRAM (logic in DRAM) semiconductor device is a device essential to making a performance of a system higher. Especially, a performance of a logic section of the logic-mixed-DRAM semiconductor device is an element having influence on the performance of the system. So, it is important to maintain the logic section in a high performance.
In the logic-mixed-DRAM semiconductor device, in order to maintain the performance of the logic section, it is necessary to form a silicide layer in a part of a diffusion layer of the logic section to thereby drop a contact resistance. On the other hand, in a DRAM section of the logic-mixed-DRAM semiconductor device, it is not necessary to form a silicide layer in a part of a diffusion layer of the DRAM section.
For this reason, conventionally, silicide block PR (photo resist) (not shown) is formed in the DRAM section so that the silicide layer is not formed in the diffusion layer of the DRAM section and the silicide layer is formed in the diffusion layer of the logic section, after the formation of a gate polysilicon layer.
As mentioned above, although the logic-mixed-DRAM semiconductor device is valuable to making the performance of the system higher, it is impossible to avoid the increase of a manufacturing cost resulting from the mixture of the DRAM and the logic. Thus, it is desirable to reduce the cost without dropping the performance of the system.
Japanese Laid Open Patent Application (JP-A-Heisei 3-8339) discloses the following method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device in which a wiring and a p-type impurity region formed on a semiconductor substrate are connected is characterized in that the method comprises: a step of selectively removing an insulating film formed on the semiconductor substrate and then forming a contact region; a step of forming a wiring layer, in which a high temperature melting point metallic silicon compound layer is laminated on a polysilicon layer, on the semiconductor substrate so as to cover the contact region; a step of patterning the wiring layer; and a step of selectively removing the high temperature melting point metallic silicon compound layer on the contact region.
Japanese Examined Patent Application (JP-B-Heisei 4-590) discloses the following method of manufacturing a bipolar type of semiconductor device. The method is characterized in that it comprises: a step of forming a lamination film pattern of a metallic silicide film and a non-mono-crystal silicon film on a part of a first conductive type of semiconductor layer; a step of doping this lamination film pattern with a second conductive type of impurity layer; a step of etching and removing only the metallic silicide film by using an etching method having a selection for metallic silicide, in a portion of the lamination film pattern, and accordingly exposing the non-mono-crystal silicon film in the portion; a step of oxidizing the exposed portion of this non-mono-crystal silicon film and thereby forming a fetching electrode; a step of diffusing the impurity from the fetching electrode into the first conductive type of semiconductor layer through a heat treatment, and thereby forming a second conductive type of high concentration impurity region; a step of selectively doping the first conductive type of semiconductor layer from an oxide region of the non-mono-crystal silicon film with a second conductive type of impurity, and thereby forming a second conductive type of low concentration impurity region adjacent to the second conductive type of high concentration impurity region; a step of leaving an insulating film in a side wall of the fetching electrode by performing an anisotropy etching on an insulating film after deposition of an insulating film to cover the fetching electrode; and a step of forming a first conductive of high concentration impurity region in the second conductive type of low concentration impurity region.